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preliminary independent clock hotlink ii? dual serializer and dual reclocking deserialize r CYV15G0204TRB cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02101 rev. ** revised july 14, 2004 features ? dual channel video serializer plus dual channel video reclocking deserializer ? 195- to 1500-mbps serial data signaling rate ? simultaneous operation at different signaling rates ? second-generation hotlink ? technology ? compliant to smpte 292 m and smpte 259m video standards ? supports reception of either 1.485 or 1.485/1.001 gbps data rate with the same training clock ? supports half-rate and full-rate clocking ? internal phase-locked loops (plls) with no external pll components ? selectable differential pecl-compatible serial inputs ? internal dc-restoration ? redundant differential pecl-compatible serial outputs ? no external bias resistors required ? signaling-rate controlled edge-rates ? internal source termination ? synchronous lvttl parallel interface ? jtag boundary scan ? built-in self-test (bist) for at-speed link testing ? link quality indicator ? analog signal detect ? digital signal detect ? low-power 2.5w @ 3.3v typical ? single 3.3v supply ? thermally enhanced bga ?0.25 bicmos technology functional description the CYV15G0204TRB independent clock hotlink ii? dual serializer and dual reclocking deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including smpte 292m and smpte 259m video applications. it supports signaling rates in the range of 195 to 1500 mbps per serial link. all transmit and receive channels are independent and can operate simultaneously at different rates. each transmit channel a ccepts 10-bit parallel characters in an input register and converts them to serial data. each receive channel accepts serial data and converts it to 10-bit parallel characters and presents t hese characters to an output register. the received serial data can also be reclocked and retransmitted through the reclocker serial outputs. figure 1 illustrates typical connections between independent video co- processors and corresponding CYV15G0204TRB chips. the CYV15G0204TRB satisfies the smpte 259m and smpte 292m compliance as per smpte eg34-1999 patho- logical test requirements. as a second-generation hotlink device, the CYV15G0204TRB extends the hotlink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and bist) with other hotlink devices. each transmit (tx) channel of the CYV15G0204TRB hotlink ii device accepts scrambled 10-bit transmission characters. these characters are serialized and output from dual positive ecl (pecl) compatible differential trans- mission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. figure 1. hotlink ii? system connections video coprocessor 10 10 10 video coprocessor 10 10 10 10 serial links independent CYV15G0204TRB independent device device channel CYV15G0204TRB channel reclocked outputs reclocked outputs
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 2 of 30 each receive (rx) channel of the CYV15G0204TRB hotlink ii device accepts a serial bit-stream from one of two selectable pecl-compatible differential line receivers, and using a completely integrated clock and data recovery pll, recovers the timing information necessary for data reconstruction. the recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. also, the recovered serial data is deserialized and presented to the destination host system. each transmit and receive channel contains an independent bist pattern generator and checker, respectively. this bist hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links. the CYV15G0204TRB is ideal for smpte applications where different data rates and serial interface standards are necessary for each channel. some applications include multi- format routers, switchers, fo rmat converters, sdi monitors, cameras, and camera control units. CYV15G0204TRB logic block diagram x10 serializer tx txda[9:0] touta1 touta2 phase align buffer refclka x10 serializer tx txdb[9:0] toutb1 toutb2 phase align buffer refclkb x10 deserializer reclocker rx rxdc[9:0] routc1 routc2 inc1 inc2 trgclkc x10 deserializer reclocker rx rxdd[9:0] routd1 routd2 ind1 ind2 trgclkd
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 3 of 30 shifter serializer path block diagram txratea input register phase-align buffer spdsela refclka+ refclka? transmit pll clock multiplier txclka bit-rate clock a character-rate clock a outa1+ outa1? outa2+ outa2? phase-align buffer transmit pll clock multiplier a oea[2..1] txcksela = internal signal txerra txclkoa txda[9:0] 10 10 pabrsta oea[2..1] 1 0 bist lfsr 10 txbista 10 shifter txrateb input register phase-align buffer spdselb refclkb+ refclkb? transmit pll clock multiplier txclkb bit-rate clock b character-rate clock b outb1+ outb1? outb2+ outb2? phase-align buffer transmit pll clock multiplier b oeb[2..1] txckselb txerrb txclkob txdb[9:0] 10 10 pabrstb oeb[2..1] 1 0 bist lfsr 10 txbistb 10 reset
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 4 of 30 reclocking deserializer path block diagram = internal signal inc1+ inc1? inc2+ inc2? inselc clock & data recovery pll shifter lfic 10 rxdc[9:0] receive signal monitor output register rxclkc+ rxclkc? 2 rxpllpdc spdselc ulcc rxratec 10 bist lfsr 10 rxbistc[1:0] ldtden sdasel[2..1]c[1:0] routc1+ routc1? routc2+ routc2? roe[2..1]c trgclkc x2 trgratec biststc character-rate clock c reclocker reclkoc register recovered character clock recovered serial data repdoc clock multiplier c output pll roe[2..1]c ind1+ ind1? ind2+ ind2? inseld clock & data recovery pll shifter lfid 10 rxdd[9:0] receive signal monitor output register rxclkd+ rxclkd? 2 rxpllpdd spdseld ulcd rxrated 10 bist lfsr 10 rxbistd[1:0] ldtden sdasel[2..1]d[1:0] routd1+ routd1? routd2+ routd2? roe[2..1]d trgclkd x2 trgrated biststd character-rate clock d reclocker reclkod register recovered character clock recovered serial data repdod clock multiplier d output pll roe[2..1]d jtag boundary scan controller tdo tms tclk tdi reset trst
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 5 of 30 wren addr[2:0] data[6:0] device configuration and control block diagram = internal signal rxrate[c..d] rxpllpd[c..d] txrate[a..b] txcksel[a..b] toe[2..1][a..b] pabrst[a..b] device configuration and control interface sdasel[2..1][c..d][1:0] rxbist[c..d][1:0] txbist[a..b] roe[2..1][c..d] trgrate[c..d]
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 6 of 30 pin configuration (top view) [1] 1. nc = do not connect. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a in c1? rout c1? in c2? rout c2? v cc in d1? rout d1? gnd in d2? rout d2? gnd tout a1? gnd gnd tout a2? v cc v cc tout b1? v cc tout b2? b in c1+ rout c1+ in c2+ rout c2+ v cc in d1+ rout d1+ gnd in d2+ rout d2+ nc tout a1+ gnd nc tout a2+ v cc nc tout b1+ nc tout b2+ c tdi tms inselc v cc v cc ulcd ulcc gnd data [6] data [4] data [2] data [0] gnd nc spd seld v cc ldtd en trst gnd tdo d tclk reset inseld v cc v cc v cc spd selc gnd data [5] data [3] data [1] gnd gnd gnd nc v cc nc v cc scan en2 tmen3 e v cc v cc v cc v cc v cc v cc v cc v cc f rx dc[8] rx dc[9] v cc v cc nc nc tx clkob nc g gnd wren gnd gnd spd selb nc spd sela nc h gnd gnd gnd gnd gnd gnd gnd gnd j gnd gnd gnd gnd nc nc nc nc k rx dc[4] trg clkc? gnd gnd nc nc nc nc l rx dc[5] trg clkc+ lfic gnd nc nc nc tx db[6] m rx dc[6] rx dc[7] v cc re pdoc ref clkb+ ref clkb? tx errb tx clkb n gnd gnd gnd gnd gnd gnd gnd gnd p rx dc[3] rx dc[2] rx dc[1] rx dc[0] tx db[5] tx db[4] tx db[3] tx db[2] r bist stc re clkoc rx clkc+ rx clkc? tx db[1] tx db[0] tx db[9] tx db[7] t v cc v cc v cc v cc v cc v cc v cc v cc u v cc v cc v cc v cc v cc rx dd[4] rx dd[3] gnd tx da[9] addr [0] trg clkd? tx da[1] gnd tx da[4] tx da[8] v cc nc tx db[8] nc nc v v cc v cc v cc rx dd[8] v cc rx dd[5] rx dd[1] gnd bist std addr [2] trg clkd+ tx clkoa gnd tx da[3] tx da[7] v cc nc nc nc nc w v cc v cc lfid rx clkd? v cc rx dd[6] rx dd[0] gnd addr [3] addr [1] nc tx erra gnd tx da[2] tx da[6] v cc nc ref clka+ nc nc y v cc v cc rx dd[9] rx clkd+ v cc rx dd[7] rx dd[2] gnd re clkod nc tx clka nc gnd tx da[0] tx da[5] v cc re pdod ref clka? nc nc
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 7 of 30 pin configuration (bottom view) [1] 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a tout b2? v cc tout b1? v cc v cc tout a2? gnd gnd tout a1? gnd rout d2? in d2? gnd rout d1? in d1? v cc rout c2? in c2? rout c1? in c1? b tout b2+ nc tout b1+ nc v cc tout a2+ nc gnd tout a1+ nc rout d2+ in d2+ gnd rout d1+ in d1+ v cc rout c2+ in c2+ rout c1+ in c1+ c tdo gnd trst ldtd en v cc spd seld nc gnd data [0] data [2] data [4] data [6] gnd ulcc ulcd v cc v cc inselc tms tdi d tmen3 scan en2 v cc nc v cc nc gnd gnd gnd data [1] data [3] data [5] gnd spd selc v cc v cc v cc inseld reset tclk e v cc v cc v cc v cc v cc v cc v cc v cc f nc tx clkob nc nc v cc v cc rx dc[9] rx dc[8] g nc spd sela nc spd selb gnd gnd wren gnd h gnd gnd gnd gnd gnd gnd gnd gnd j nc nc nc nc gnd gnd gnd gnd k nc nc nc nc gnd gnd trg clkc? rx dc[4] l tx db[6] nc nc nc gnd lfic trg clkc+ rx dc[5] m tx clkb tx errb ref clkb? ref clkb+ re pdoc v cc rx dc[7] rx dc[6] n gnd gnd gnd gnd gnd gnd gnd gnd p tx db[2] tx db[3] tx db[4] tx db[5] rx dc[0] rx dc[1] rx dc[2] rx dc[3] r tx db[7] tx db[9] tx db[0] tx db[1] rx clkc? rx clkc+ re clkoc bist stc t v cc v cc v cc v cc v cc v cc v cc v cc u nc nc tx db[8] nc v cc tx da[8] tx da[4] gnd tx da[1] trg clkd? addr [0] tx da[9] gnd rx dd[3] rx dd[4] v cc v cc v cc v cc v cc v nc nc nc nc v cc tx da[7] tx da[3] gnd tx clkoa trg clkd+ addr [2] bist std gnd rx dd[1] rx dd[5] v cc rx dd[8] v cc v cc v cc w nc nc ref clka+ nc v cc tx da[6] tx da[2] gnd tx erra nc addr [1] addr [3] gnd rx dd[0] rx dd[6] v cc rx clkd? lfid v cc v cc y nc nc ref clka? re pdod v cc tx da[5] tx da[0] gnd nc tx clka nc re clkod gnd rx dd[2] rx dd[7] v cc rx clkd+ rx dd[9] v cc v cc
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 8 of 30 pin definitions CYV15G0204TRB hotlink ii dual serializer and dual reclocking deserializer name i/o characteris- tics signal description transmit path data and status signals txda[7:0] txdb[7:0] lvttl input, synchronous, sampled by the associated txclkx or refclkx [2] transmit data inputs . txdx[9:0] data inputs are captured on the rising edge of the transmit interface clock. the transmit interface clock is selected by the txckselx latch via the device configuration interface. txerra txerrb lvttl output, synchronous to refclkx [3] , asynchronous to transmit channel enable / disable, asynchronous to loss or return of refclkx transmit path error . txerrx is asserted high to indicate detection of a transmit phase-align buffer underflow or overflow. if an underflow or overflow condition is detected, txerrx, for the channel in erro r, is asserted high and remains asserted until the transmit phase-align buffer is re -centered with the pabrstx latch via the device configuration interface. when txbi stx = 0, the bist progress is presented on the associated txerrx output. the txerrx signal pulses high for one transmit-character clock period to indi cate a pass through the bist sequence once every 511 character times. txerrx is also asserted high, when any of the following conditions is true: ? the txpll for the associated channel is powered down. this occurs when oe2x and oe1x for a given channel are both disabl ed by setting oe2x = 0 and oe1x = 0. ? the absence of the refclkx signal. transmit path clock signals refclka refclkb differential lvpecl or single-ended lvttl input clock reference clock . refclkx clock inputs are used as the timing references for the transmit pll. these i nput clocks may also be sele cted to clock the transmit parallel interface. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either t he true or complement refclkx input, and leave the alternate refclkx input open (f loating). when driven by an lvpecl clock source, the clock must be a differential clock, using both inputs. txclka txclkb lvttl clock input, internal pull-down transmit path input clock . when configuration latch txckselx = 0, the associated txclkx input is selected as the character-rate input clock for the txdx[9:0] input. in this mode, the txclkx input must be frequency-coherent to its associated txclkox output clock, but may be offset in phase by any amount. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phase align buffer, txerrx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx input clock relative to its associated refclkx is initialized when the configuration latch pabrstx is written as 0. when the as sociated txerrx is deasserted, the phase align buffer is initialized and input charac ters are correctly captured. txclkoa txclkob lvttl output transmit clock output . txclkox output clock is syn thesized by each channel?s transmit pll and operates synchronous to the internal transmit character clock. txclkox operates at either the same frequency as refclkx (txratex = 0), or at twice the frequency of refclkx (txr atex = 1). the transmit clock outputs have no fixed phase relationship to refclkx. notes: 2. when refclkx is configured for half-rate operation, these i nputs are sampled relative to both the rising and falling edges o f the associated refclkx. 3. when refclkx is configured for half-rate operation, these outputs are presented relative to both the rising and falling edge s of the associated refclkx.
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 9 of 30 receive path data and status signals rxdc[9:0] rxdd[9:0] lvttl output, synchronous to the rxclk output parallel data output . rxdx[9:0] parallel data outputs change relative to the receive interface clock. if rxclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks ope rating at the character ra te. the rxdx[9:0] outputs for the associated receive channels follow rising edge of rxclkx+ or falling edge of rxclkx?. if rxclkx is a half-rate clock, the rxclkx clock outputs are complementary clocks operating at half th e character rate. the rxdx[9:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclkx clock outputs. when bist is enabled on the receive channel , the bist status is presented on the rxdx[1:0] and biststx outputs. see table 6 for each status reported by the bist state machine. also, while bist is enabled, the rxdx[9:2] outputs should be ignored. biststc biststd lvttl output, synchronous to the rxclkx output bist status output. when rxbistx[1:0] = 10, bist stx (along with rxdx[1:0]) displays the status of the bist reception. see table 6 for the bist status reported for each combination of biststx and rxdx[1:0]. when rxbistx[1:0] 10, biststx should be ignored. repdoc repdod asynchronous to reclocker output channel enable / disable reclocker powered down status output. repdox is asserted high, when the associated channel?s reclocker output logic is powered down. this occurs when roe2x and roe1x are both disabled by setting roe2x = 0 and roe1x = 0. receive path clock signals trgclkc trgclkd differential lvpecl or single-ended lvttl input clock cdr pll training clock . trgclkx clock inputs are used as the reference source for the frequency detector (range co ntroller) of the associated receive pll to reduce pll acquisition time. in the presence of valid serial data, th e recovered clock output of the receive cdr pll (rxclkx) has no frequency or phase relationship with trgclkx. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or compleme nt trgclkx input, and leave the alternate trgclkx input open (floatin g). when driven by an lvpec l clock source, the clock must be a differential clock, using both inputs. rxclkc rxclkd lvttl output clock receive clock output . rxclkx is the receive interface clock used to control timing of the rxdx[9:0] parallel outputs. these true and complement clocks are used to control timing of data output transfers. thes e clocks are output continuously at either the half-character rate (1/20 th the serial bit-rate) or character rate (1/10 th the serial bit-rate) of the data bein g received, as selected by rxratex. reclkoc reclkod lvttl output reclocker clock output . reclkox output clock is syn thesized by the associated reclocker output pll and operates synchronous to the internal recovered character clock. reclkox operates at either the same frequency as rxclkx (rxratex = 0), or at twice the frequency of rxclkx (rxratex = 1).the reclocker clock outputs have no fixed phase relationship to rxclkx. device control signals reset lvttl input, asynchronous, internal pull-up asynchronous device reset . reset initializes all state machines, counters, and configuration latches in the device to a known state. reset must be asserted low for a minimum pulse width. when the reset is removed, all state machines, counters and configuration latches are at an initial state. see ta ble 4 for the initialize values of the device configuration latches. pin definitions (continued) CYV15G0204TRB hotlink ii dual serializer and dual reclocking deserializer name i/o characteris- tics signal description
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 10 of 30 ldtden lvttl input, internal pull-up level detect transition density enable . when ldtden is high, the signal level detector, range controller, and transition density detector are all enabled to determine if the rxpll tracks trgclkx or the selected input serial data stream. if the signal level detector, range controller, or transition density detector are out of their respective limits while ldtden is high, the rxpll locks to trgclkx until such a time they become valid. the sdasel[a..d][1:0] inputs are used to configure the trip level of the signal level detector. the transition density detector limit is one transition in every 60 consecutive bits. when ldtden is low, only the range controller is used to determine if the rxpll tracks trgclkx or the selected input serial data stream. it is recommended to set ldtden = high. ulcc ulcd lvttl input, internal pull-up use local clock . when ulcx is low, the rxpll is forced to lock to trgclkx instead of the received serial data stream. while ulcx is low, the lfix for the associated channel is low indicating a link fault. when ulcx is high, the rxpll performs clock and data recovery functions on the input data streams. this function is used in applications in which a stable rxclkx is needed. in cases when there is an absence of valid data transitions for a long period of time, or the high-gain differ ential serial inputs (inx) are left floating, there may be brief frequency excursions of the rxclkx outputs from trgclkx. spdsela spdselb spdselc spdseld 3-level select [4] static control input serial rate select . the spdselx inputs specify the operating signaling-rate range of each channel?s transmit (channels a and b) or receive pll (channels c and d). low = 195 ? 400 mbd mid = 400 ? 800 mbd high = 800 ? 1500 mbd. inselc inseld lvttl input, asynchronous receive input selector . the inselx input determines which external serial bit stream is passed to the receiver?s clo ck and data recovery circuit. when inselx is high, the primary differential serial data input, inx1, is selected for the associated receive channel. when inselx is low, the secondary differential serial data input, inx2, is selected for the associated receive channel. lfic lfid lvttl output, asynchronous link fault indication output . lfix is an output status indicator signal. lfix is the logical or of six internal conditions. lfix is asserted low when any of the following conditions is true: ? received serial data rate outside expected range ? analog amplitude below expected levels ? transition density lower than expected ? receive channel disabled ?ulcx is low ? absence of trgclkx. device configuration and control bus signals wren lvttl input, asynchronous, internal pull-up control write enable . the wren input writes the values of the data[6:0] bus into the latch specified by the addre ss location on the addr[3:0] bus. [5] addr[3:0] lvttl input asynchronous, internal pull-up control addr essing bus . the addr[3:0] bus is the input address bus used to configure the device. the wren input writes the values of the data[6:0] bus into the latch specified by the addres s location on the addr[3:0] bus. [5] ta ble 4 lists the configuration latches within the device, and the initialization value of the latches upon the assert ion of reset . table 5 shows how the latches are mapped in the device. notes: 4. 3-level select inputs are used for static configuration. these ar e ternary inputs that make use of logic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually im plemented by direct connection to v cc (power). the mid level is usually implemented by not conn ecting the input (left floating), which allows it to self bias to the proper level. 5. see device configuration and control interface for detailed information on the operation of the configuration interface. pin definitions (continued) CYV15G0204TRB hotlink ii dual serializer and dual reclocking deserializer name i/o characteris- tics signal description
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 11 of 30 data[6:0] lvttl input asynchronous, internal pull-up control data bus . the data[6:0] bus is the input data bus used to configure the device. the wren input writes the values of t he data[6:0] bus into the latch specified by address location on the addr[3:0] bus. [5 ] table 4 lists the configu- ration latches within the device, and the init ialization value of the latches upon the assertion of reset . table 5 shows how the latches are mapped in the device. internal device configuration latches rxrate[c..d] internal latch [6] receive clock rate select . sdasel[2..1][c.. d] [1:0] internal latch [6] signal detect amplitude select . txcksel[a..b] internal latch [6] transmit clock select . txrate[a..b] internal latch [6] transmit pll clock rate select . trgrate[c..d] internal latch [6] reclocker output pll clock rate select . rxpllpd[c..d] internal latch [6] receive channel power control . rxbist[c..d][1:0] internal latch [6] receive bist disabled . txbist[a..b] internal latch [6] transmit bist disabled . toe2[a..b] internal latch [6] transmitter different ial serial output driver 2 enable . toe1[a..b] internal latch [6] transmitter different ial serial output driver 1 enable . roe2[c..d] internal latch [6] reclocker differential serial output driver 2 enable . roe1[c..d] internal latch [6] reclocker differential serial output driver 1 enable . pabrstb[a..b] internal latch [6] transmit clock phase alignment buffer reset . factory test modes scanen2 lvttl input, internal pull-down factory test 2. scanen2 input is for factory testing only. this input may be left as a no connect, or gnd only. tmen3 lvttl input, internal pull-down factory test 3 . tmen3 input is for factory testing only. this input may be left as a no connect, or gnd only. analog i/o touta1 toutb1 cml differential output transmitter primary differential serial data output . the transmitter toutx1 pecl-compatible cml outputs (+3.3v refe renced) are capable of driving termi- nated transmission lines or standard fibe r-optic transmitter modules, and must be ac-coupled for pecl-compatible connections. touta2 toutb2 cml differential output transmitter secondary differential serial data output . the transmitter toutx2 pecl-compatible cml outputs (+3.3v refer enced) are capable of driving terminated transmission lines or standard fiber-optic transmitt er modules, and must be ac-coupled for pecl-compatible connections. routc1 routd1 cml differential output reclocker primary differential serial data output . the reclocker routx1 pecl-compatible cml outputs (+3.3v refe renced) are capable of driving termi- nated transmission lines or standard fibe r-optic transmitter modules, and must be ac-coupled for pecl-compatible connections. routc2 routd2 cml differential output reclocker secondary differential serial data output . the reclocker routx2 pecl-compatible cml outputs (+3.3v refer enced) are capable of driving terminated transmission lines or standard fiber-optic transmitt er modules, and must be ac-coupled for pecl-compatible connections. inc1 ind1 differential input primary differential serial data input . the inx1 input accepts the serial data stream for deserialization. the inx1 serial stream is passed to the receive cdr circuit to extract the data content when inselx = high. inc2 ind2 differential input secondary differential serial data input . the inx2 input accepts the serial data stream for deserialization. the inx2 seri al stream is passed to the receiver cdr circuit to extract the data content when inselx = low. note: 6. see device configuration and control interface for detailed information on the internal latches. pin definitions (continued) CYV15G0204TRB hotlink ii dual serializer and dual reclocking deserializer name i/o characteris- tics signal description
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 12 of 30 CYV15G0204TRB hotlink ii operation the CYV15G0204TRB is a highly configurable, independent clocking, device designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. CYV15G0204TRB transmit data path input register the parallel input bus txdx[9:0] can be clocked in using txclkx (txckselx = 0) or refclkx (txckselx = 1). phase-align buffer data from each input register is passed to the associated phase-align buffer, when the txdx[9:0] input registers are clocked using txclkx (txckselx = 0 and txratex = 0). when the txdx[9:0] input registers are clocked using refclkx (txckselx = 1) and refclkx is a full-rate clock, the associated phase a lignment buffer in the transmit path is bypassed. these buffers are used to absorb clock phase differences between the txclkx input clock and the internal character clock for that channel. once initialized, txclkx is allowed to drift in phase as much as 180 degrees. if the input phase of txclkx drifts beyond the handling capacity of the phase align buffer, txerrx is asserted to indicate the loss of data, and remains asserted until the phase align buffer is initialized. the phase of the txclkx relative to its associated internal character rate clock is initialized when the configuration latch pabrstx is written as 0. when the associated txe rrx is deasserted, the phase align buffer is initialized and input characters are correctly captured. if the phase offset, between the initialized location of the input clock and refclkx, exceeds the skew handling capabilities of the phase-align buffer, an error is reported on that channel?s txerrx output. this output indicates an error continuously until the phase-align buffer for that channel is reset. while the error remains active, the transmitter for that channel outputs a continuous ?1001111000? character to indicate to the remote receiver that an error condition is present in the link. transmit bist each transmit channel contains an internal pattern generator that can be used to validate both the link and device operation. these generators are enabled by the associated txbistx latch via the device configuration interface. when enabled, a register in the associated transmit channel becomes a signature pattern generator by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511- character sequence. this provides a predictable yet pseudo- random sequence that can be matched to an identical lfsr in the attached receiver(s). a device reset (reset sampled low) presets the bist enable latches to disable bist on both channels. all data present at the associated txdx[9:0] inputs are ignored when bist is active on that channel. transmit pll clock multiplier each transmit pll clock multip lier accepts a character-rate or half-character-rate external clock at the associated refclkx input, and that clock is multiplied by 10 or 20 (as selected by txratex) to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as txclkox. each clock multiplier pll can accept a refclkx input between 19.5 mhz and 150 mhz, however, this clock range is limited by the operating mode of the CYV15G0204TRB clock multiplier (txratex) and by the level on the associated spdselx input. spdselx are 3-level select [4] inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel. the operating serial signaling-rate and jtag interface tms lvttl input, internal pull-up test mode select . used to control access to the jtag test modes. if maintained high for 5 tclk cycles, the jtag test controller is reset. tclk lvttl input, internal pull-down jtag test clock . tdo 3-state lvttl output test data out . jtag data output buffer. high-z while jtag test mode is not selected. tdi lvttl input, internal pull-up test data in . jtag data input port. trst lvttl input, internal pull-up jtag reset signal . when asserted (low), this input asynchronously resets the jtag test access port controller. power v cc +3.3v power . gnd signal and power ground for all internal circuits . pin definitions (continued) CYV15G0204TRB hotlink ii dual serializer and dual reclocking deserializer name i/o characteris- tics signal description
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 13 of 30 allowable range of refclkx frequencies are listed in table 1 . the refclkx inputs are differential inputs with each input internally biased to 1.4v. if the refclkx+ input is connected to a ttl, lvttl, or lvcmos clock source, the input signal is recognized when it passes through the internally biased reference point. when driven by a single-ended ttl, lvttl, or lvcmos clock source, connec t the clock source to either the true or complement refclkx input, and leave the alternate refclkx input open (floating). when both the refclkx+ and refclkx? inputs are connected, the clock source must be a differential clock. this can either be a differential lvpecl clock that is dc-or ac-coupled or a differential lvttl or lvcmos clock. by connecting the refclkx? input to an external voltage source, it is possible to adjust the reference point of the refclkx+ input for alternate logic levels. when doing so, it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. transmit serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for 50 ? transmission lines. these drivers accept data from the transmit shifters. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. transmit channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. note . when a disabled transmit channel (i.e., both outputs disabled) is re-enabled: ? data on the serial outputs may not meet all timing specifi- cations for up to 250 s ? the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used CYV15G0204TRB receive data path serial line receivers two differential line receivers, inx1 and inx2, are available on each channel for accepting serial data streams. the active serial line receiver on a channel is selected using the associated inselx input. the serial line receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16 db. for normal operation, these inputs should receive a signal of at least vi diff > 100 mv, or 200 mv peak-to-peak differential. each line receiver can be dc- or ac-coupled to +3.3v powered fiber-optic interface modules (any ecl/pecl family, not limited to 100k pecl) or ac-coupled to +5v powered optical modules. the common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. each receiver provides internal dc- restoration, to the center of the receiver?s common mode range, for ac-coupled signals. signal detect/link fault each selected line receiver (i.e., that routed to the clock and data recovery pll) is simultaneously monitored for ? analog amplitude above amplitude level selected by sdaselx ? transition density above the specified limit ? range controls report the received data stream inside normal frequency range (1500ppm [23] ) ? receive channel enabled ? presence of reference clock ?ulcx is not asserted. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfix (link fault indicator) output associated with each receive channel, which changes synchronous to the receive interface clock. analog amplitude while most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high-noise environments. the analog amplitude level detection is set by the sdaselx latch via device configuration interface. the sdaselx latch sets the trip point for the detection of a valid signal at one of three levels, as listed in table 2 . this control input affects the analog monitors for both receive channels. the analog signal detect monitors are active for the line receiver as selected by the associated inselx input. transition density the transition detection logi c checks for the absence of transitions spanning greater than six transmission characters table 1. operating speed settings spdselx txratex refclkx frequency (mhz) signaling rate (mbps) low 1 reserved 195 ? 400 0 19.5 ? 40 mid (open) 1 20 ? 40 400 ? 800 0 40 ? 80 high 1 40 ? 75 800 ? 1500 0 80 ? 150 table 2. analog amplitude detect valid signal levels [7] sda- sel typical signal with peak amplitudes above 00 analog signal detector is disabled 01 140 mv p-p differential 10 280 mv p-p differential 11 420 mv p-p differential
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 14 of 30 (60 bits). if no transitions are present in the data received, the detection logic for that channel asserts lfix . range controls the cdr circuit includes logic to monitor the frequency of the pll voltage controlled oscillator (vco) used to sample the incoming data stream. this logic ensures that the vco operates at, or near the rate of the incoming data stream for two primary cases: ? when the incoming data stream resumes after a time in which it has been ?missing.? ? when the incoming data stream is outside the acceptable signaling rate range. to perform this function, t he frequency of the rxpll vco is periodically compared to the frequency of the trgclkx input. if the vco is running at a frequency beyond 1500ppm [23] as defined by the trgclkx frequency, it is periodically forced to the correct frequency (as defined by trgclkx, spdselx, and trgratex) and then released in an attempt to lock to the input data stream. the sampling and relock period of the range control is calcu- lated as follows: range_control_ sampling_period = (recovered byte cl ock period) * (4096). during the time that the range control forces the rxpll vco to track trgclkx, the lfix output is asserted low. after a valid serial data stream is applied, it may take up to one range control sampling period before the pll locks to the input data stream, after which lfix should be high. the operating serial signaling-rate and allowable range of trgclk frequencies are listed in table 1 . receive channel enabled the CYV15G0204TRB contains two receive channels that can be independently enabled and disabled. each channel can be enabled or disabled separately through the rxpllpdx input latch as controlled by the device configuration interface. when the rxpllpdx latch = 0, the associated pll and analog circuitry of the channel is disabled. any disabled channel indicates a constant link fault condition on the lfix output. when rxpllpdx = 1, the associated pll and receive channel is enabled to receive a serial stream. when a disabled receive channel is reenabled, the status of the associated lfix output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. clock/data recovery the extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate cdr block within each receive channel. the clock extraction function is performed by an integrated p ll that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit-rate clock to the transitions in the selected serial data stream. each cdr accepts a character-rate (bit-rate 10) or half- character-rate (bit-rate 20) training clock from the associated trgclkx input. this trgclkx input is used to ? ensure that the vco (within the cdr) is operating at the correct frequency (rather than a harmonic of the bit-rate) ? reduce pll acquisition time ? limit unlocked frequency excursions of the cdr vco when there is no input data present at the selected serial line receiver. regardless of the type of signa l present, the cdr attempts to recover a data stream from it. if the signalling rate of the recovered data stream is outside the limits set by the range control monitors, t he cdr tracks trgclkx instead of the data stream. once the cdr output (rxclk) frequency returns back close to trgclkx frequency, the cdr input is switched back to the input data stream. if no data is present at the selected line receiver, this switching behavior may result in brief rxclk frequency excursions from trgclkx. however, the validity of the input data stream is indicated by the lfix output. the frequency of trgclkx is required to be within 1500ppm [23] of the frequency of the clock that drives the refclkx input of the remote transmitter to ensure a lock to the incoming data stream. this large ppm tolerance allows the cdr pll to reliably receive a 1.485 or 1.485/1.001 gbps smpte hd-sdi data stream with a constant trgclk frequency. for systems using multiple or redundant connections, the lfix output can be used to select an alternate data stream. when an lfix indication is detected, external logic can toggle selection of the associated inx1 and inx2 input through the associated inselx input. when a port switch takes place, it is necessary for the receive pll for that channel to reacquire the new serial stream. reclocker each receive channel performs a reclocker function on the incoming serial data. to do this, the clock and data recovery pll first recovers the clock from the data. the data is retimed by the recovered clock and then passed to an output register. also, the recovered character clock from the receive pll is passed to the reclocker output pll which generates the bit clock that is used to clock the retimed data into the output register. this data stream is then transmitted through the differential serial outputs. note: 7. the peak amplitudes listed in this table are for typical wave forms that have generally 3 ? 4 transitions for every ten bits. in a worse case environment the signals may have a sine-wave appearance (highest transition density with repeating 0101...). signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mv. table 3. operating speed settings spdselx trgratex trgclkx frequency (mhz) signaling rate (mbps) low 1 reserved 195 ? 400 0 19.5 ? 40 mid (open) 1 20 ? 40 400 ? 800 0 40 ? 80 high 1 40 ? 75 800 ? 1500 0 80 ? 150
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 15 of 30 reclocker serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for 50 ? transmission lines. these drivers accept data from the reclocker output register in the reclocker channel. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. reclocker output channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both reclocker serial drivers for a channel are in this disabled state, the associated internal reclocker logic is also powered down. the deserialization logic and parallel outputs will remain enabled. a device reset (reset sampled low) disables all output drivers. note . when the disabled reclocker function (i.e., both outputs disabled) is re-enabled, the data on the reclocker serial outputs may not meet all timing specifications for up to 250 s. output bus the receive channel presents a 10-bit data signal (and a bist status signal when rxbistx[1:0] = 10). receive bist operation each receiver channel contains an internal pattern checker that can be used to validate both device and link operation. these pattern checkers are enabled by the associated rxbistx[1:0] latch via the de vice configurat ion interface. when enabled, a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character sequence. this provides a predictable yet pseudo-random sequence that can be matched to an identical lfsr in the attached trans- mitter(s). when synchronized with the received data stream, the associated receiver che cks each character from the deserializer with each character generated by the lfsr and indicates compare errors and bist status at the rxdx[1:0] and biststx bits of the output register. the bist status bus {biststx, rxdx[0], rxdx[1]} indicates 010b or 100b for one character period per bist loop to indicate loop completion. this status can be used to check test pattern progress. if the number of invalid characters received ever exceeds the number of valid characters by 16, the receive bist state machine aborts the compare operations and resets the lfsr to look for the start of the bist sequence again. a device reset (reset sampled low) presets the bist enable latches to disable bist on both channels. bist status state machine when a receive path is enabled to look for and compare the received data stream with the bist pattern, the {biststx, rxdx[0], rxdx[1]} bits identify the present state of the bist compare operation. the bist state machine has multiple states, as shown in figure 2 and table 6 . when the receive pll detects an out-of- lock condition, the bist state is forced to the start-of-bist state, regardless of the pres ent state of the bist state machine. if the number of detected errors ever exceeds the number of valid matches by great er than 16, the state machine is forced to the wait_for_bist state where it monitors the receive path for the first character of the next bist sequence. power control the CYV15G0204TRB supports user control of the powered up or down state of each transmit and receive channel. the receive channels are controlled by the rxpllpdx latch via the device configuration interface. when rxpllpdx = 0, the associated pll and analog circuitry of the channel is disabled. the transmit channels are controlled by the toe1x and the toe2x latches via the device configuration interface. the reclocker function is controlled by the roe1x and the roe2x latches via the device configuratio n interface. when a driver is disabled via the configuration interf ace, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. when the reclocker serial drivers are disabled, the reclocker function will be disabled, but the deserialization logic and parallel outputs will remain enabled. device reset state when the cyv 15g0204trb is reset by assertion of reset , all state machines, counters, and configuration latches in the device are initialized to a reset state. see table 4 for the initialize values of the configuration latches. following a device reset, it is necessary to enable the receive channels used for normal operation. this can be done by sequencing the appropriate values on the device configuration interface. [5] device configuration and control interface the CYV15G0204TRB is highly configurable via the configu- ration interface. the configur ation interface allows each channel to be configured independently. table 4 lists the configuration latches within the device including the initial- ization value of the latches upon the assertion of reset . table 5 shows how the latches are mapped in the device. each row in the table 5 maps to a 7-bit latch bank. there are 12 such write-only latch banks. when wren = 0, the logic value in the data[7:0] is latched to the latch bank specified by the values in addr[3:0]. the second column of table 5 specifies the channels associated with the corresponding latch bank. for example, the first three latch banks (0,1 and 2) consist of configuration bits for channel a. latch types there are two types of latch banks: static (s) and dynamic (d). each channel is configured by 2 static and 1 dynamic latch banks. the s type contain those settings that normally do not change for a given application, whereas the d type controls the settings that could change during the applicat ion's lifetime. the first and second rows of each channel (address numbers 0, 1, 3, 4, 6, 7, 9, and 10) ar e the static control latches. the third row of latches for each channel (address numbers 2, 5, 8, and 11) are the dynamic contro l latches that are associated with enabling dynamic functions within the device.
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 16 of 30 static latch values there are some latches in the table that have a static value (i.e.. 1, 0, or x). the latches that have a ?1? or ?0? must be configured with their corresponding value each time that their associated latch bank is confi gured. the latches that have an ?x? are don?t cares and can be configured with any value. table 4. device configuration and control latch descriptions name signal description txcksela txckselb transmit clock select . the initialization value of the txckselx latch = 1. txckselx selects the clock source used to write data into the transmit inpu t register. when txckselx = 1, the associated input register txdx[9:0] is clocked by refclkx . in this mode, the phase alignment buffer in the transmit path is bypassed. when txckselx = 0, the associated txclkx is used to clock in the input register txdx[9:0]. txratea txrateb transmit pll clock rate select . the initialization value of the tx ratex latch = 0. txratex is used to select the clock multip lier for the transmit pll. when txratex = 0, each transmit pll multiples the associated refclkx input by 10 to generate the serial bit-rate clock. when txratex = 0, the txclkox output clocks are full-rate clocks and follow the frequency and duty cycl e of the associated refclkx input. when txratex = 1, each transmit pll multiplies the associated refclkx input by 20 to generate the serial bit-rate clock. when txratex = 1, the txclkox output clocks are twice the frequency rate of the refclk x input. when txclkselx = 1 and txratex = 1, the transmit data inputs are captured using both the rising and falling edges of refclkx. txratex = 1 and spdselx = low, is an invalid state and this combination is reserved. txbista txbistb transmit bist disabled . the initialization value of the txbistx la tch = 1. txbistx sele cts if the transmit bist is disabled or enabled. when txbistx = 1, th e transmit bist function is disabled. when txbistx = 0, the transmit bist function is enabled. toe2a toe2b secondary differential serial data output driver enable . the initialization value of the toe2x latch = 0. toe2x selects if the toutx2 secondary different ial output drivers are enabled or disabled. when toe2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when toe2x = 0, the associated seri al data output driver is disabled. when a driver is disabled via the configuration interface, it is inte rnally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampl ed low) disables all output drivers. toe1a toe1b primary differential serial data output driver enable . the initialization value of the toe1x latch = 0. toe1x selects if the toutx1 primary differenti al output drivers are enabled or disabled. when toe1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when toe1x = 0, the associated seri al data output driver is disabled. when a driver is disabled via the configuration interface, it is inte rnally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampl ed low) disables all output drivers. pabrsta pabrstb transmit clock phase alignment buffer reset . the initialization value of the pabrstx latch = 1. the pabrstx is used to re-center the transmit phase align buffer. when the configuration latch pabrstx is written as a 0, the phase of the txclkx input clock relative to its associated refclkx+/- is initialized. pabrst is an asynchronous input, but is sampled by each txclkx to synchronize it to the internal clock domain. pabrstx is a self clearing latch. this el iminates the requirement of writing a 1 to complete the initialization of the phase alignment buffer. rxratec rxrated receive clock rate select . the initialization value of the rxra tex latch = 1. rxratex is used to select the rate of the rxclkx clock output. when rxratex = 1 , the rxclkx clock outputs are complementary clocks t hat follow the recovered clock operating at half the character rate. data for the associated receive channels should be latched alternately on the rising e dge of rxclkx+ and rxclkx?. when rxratex = 0 , the rxclkx clock outputs are complementary clocks t hat follow the recovered clock operating at the character rate. data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx?. sdasel1c[1:0] sdasel1d[1:0] primary serial data input sign al detector amplitude select . the initialization value of the sdasel1x[1:0] latch = 10. sdasel 1x[1:0] selects the trip point for the detection of a valid signal for the inx1 primary differential serial data inputs. when sdasel1x[1:0] = 00, the analog signal detector is disabled. when sdasel1x[1:0] = 01, the typical p-p differential voltage threshold level is 140mv. when sdasel1x[1:0] = 10, the typical p-p differential voltage threshold level is 280mv. when sdasel1x[1:0] = 11, the typical p-p differential voltage threshold level is 420mv.
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 17 of 30 device configuration strategy the following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. pulse reset low after device power-up. this operation resets all four channels. 2. set the static latch banks for the target channel. 3. set the dynamic bank of latches for the target channel. enable the receive plls and transmit channels. if a receive channel is enabled, set the channel for smpte data reception (rxbista[1:0] = 01 ) or bist data reception (rxbista[1:0] = 10). 4. reset the phase alignment buffer for the target channel. [optional if phase align buffer is bypassed.] sdasel2c[1:0] sdasel2d[1:0] secondary serial data input si gnal detector amplitude select . the initialization value of the sdasel2x[1:0] latch = 10. sdasel 2x[1:0] selects the trip point for the detection of a valid signal for the inx2 secondary differential serial data inputs. when sdasel2x[1:0] = 00, the analog signal detector is disabled when sdasel2x[1:0] = 01, the typical p-p differential voltage threshold level is 140mv. when sdasel2x[1:0] = 10, the typical p-p differential voltage threshold level is 280mv. when sdasel2x[1:0] = 11, the typical p-p differential voltage threshold level is 420mv. trgratec trgrated training clock rate select . the initialization value of the trgratex latch = 0. trgratex is used to select the clock multiplier for the training cloc k input to the associated cdr pll. when trgratex = 0, the trgclkx input is not multiplied before it is passed to the cdr pll. when trgratex = 1, the trgclkx input is multiplied by 2 before it is passed to the cdr pll. trgratex = 1 and spdselx = low is an invalid state and this combination is reserved. rxpllpdc rxpllpdd receive channel enable . the initialization value of the rxpllpdx latch = 0. rxpllpdx selects if the associated receive channel is enabled or powered-down. when rxpllpdx = 0, the associated receive pll and analog circuitry are powered-down. when rxpllpdx = 1, the associated receive pll and analog circuitry are enabled. rxbistc[1:0] rxbistd[1:0] receive bist disable / smpte receive enable . the initialization value of the rxbistx[1:0] latch = 11. for smpte data reception, rxbistx[1:0] shoul d not remain in this initialization state (11). rxbistx[1:0] selects if receive bist is disabled or enabled and sets the associated channel for smpte data reception. when rxbistx[1:0] = 01, the receiver bist function is disabled and the associated channel is set to receive smpte data. when rxbistx[ 1:0] = 10, the receive bi st function is enabled and the associated channel is set to receive bist data. rxbistx[1:0] = 00 and rxbistx[1:0] = 11 are invalid states. roe2c roe2d reclocker secondary differential serial data output driver enable . the initialization value of the roe2x latch = 0. roe2x selects if the routx2 se condary differential output drivers are enabled or disabled. when roe2x = 1, the associated serial da ta output driver is enabled allowing data to be transmitted from the transmit shifter. when roe2x = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. roe1c roe1d reclocker primary diffe rential serial data output driver enable . the initialization value of the roe1x latch = 0. roe1x selects if the routx1 pr imary differential output drivers are enabled or disabled. when roe1x = 1, the associated serial da ta output driver is enabled allowing data to be transmitted from the transmit shifter. when roe1x = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (reset sampled low) disables all output drivers. table 4. device configuration and control latch descriptions (continued)
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 18 of 30 jtag support the CYV15G0204TRB contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, boundary scan, and bypass are supported. this capability is present only on the lvttl inputs and outputs, the refclkx clock inputs, and th e trgclkx clock inputs. the high-speed serial inputs and outputs are not part of the jtag test chain. 3-level select inputs each 3-level select inputs reports as two bits in the scan register. these bits report t he low, mid, and high state of the associated input as 00, 10, and 11 respectively jtag id the jtag device id for the CYV15G0204TRB is ?0c811069?x. table 5. device control latch configuration table addr channel type data6 data5 data4 data3 data2 data1 data0 reset value 0 (0000b) a s x x x x x 0 x 1011111 1 (0001b) a s x x x x 0 txcksela txratea 1010110 2 (0010b) a d x x x txbista oe2a oe1a pabrsta 1011001 3 (0011b) b s x x x x x 0 x 1011111 4 (0100b) b s x x x x 0 txckselb txrateb 1010110 5 (0101b) b d x x x txbistb oe2b oe1b pabrstb 1011001 6 (0110b) c s 1 0 x x 0 0 rxratec 1011111 7 (0111b) c s sdasel2c[1] sdasel2c[0] sdasel1c[1] sdasel1c[0] x x trgratec 1010110 8 (1000b) c d rxbistc[1] rxpllpdc rxbistc[0] x roe2c roe1c x 1011001 9 (1001b) d s 1 0 x x 0 0 rxrated 1011111 10 (1010b) d s sdasel2d[1] sdasel2d[0] sdasel1d[1] sdasel1d[0] x x trgrated 1010110 11 (1011b) d d rxbistd[1] rxpllpdd rxbistd[0] x roe2d roe1d x 1011001 12 (1100b) internal test registers do not write to these addresses 13 (1101b) 14 (1110b) 15 (1111b) table 6. receive character status bits {biststx, rxdx[0], rxdx[1]} description receive bist status (receive bist = enabled) 000, 001 bist data compare . character compared correctly. 010 bist last good . last character of bist sequence detected and valid. 011 reserved. 100 bist last bad . last character of bist sequence detected invalid. 101 bist start . receive bist is enabled on this cha nnel, but character compares have not yet commenced. this also indicates a pll out of lock condition. 110 bist error . while comparing characters, a mismatch was found in one or more of the character bits. 111 bist wait . the receiver is comparing characters. but has not yet found the start of bist character to enable the lfsr.
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 19 of 30 receive bist detected low monitor data received {biststx, rxdx[0], no rx pll out of lock yes, {biststx, rxdx[0], rxdx[1]} = bist_data_compare (000, 001) compare next character auto-abort condition mismatch end-of-bist state yes, {biststx, rxdx[0], rxdx[1]} = bist_last_bad (100) yes no no, {biststx, rxdx[0], rxdx[1]} = bist_error (110) match end-of-bist state yes, {biststx, rxdx[0], rxdx[1]} = bist_last_good (010) no {biststx, rxdx[0], rxdx[1]} = bist_data_comp are (000, 001) figure 2. receive bist state machine start of bist detected {biststx, rxdx[0], rxdx[1]} = bist_wait (111) bist_start (101) rxdx[1]} =
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 20 of 30 maximum ratings (above which the useful life may be impaired. user guidelines only, not tested.) storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +3.8v dc voltage applied to lvttl outputs in high-z state .......................................?0.5v to v cc + 0.5v output current into lvttl outputs (low)..................60 ma dc input voltage....................................?0.5v to v cc + 0.5v static discharge voltage.......................................... > 2000 v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma power-up requirements the CYV15G0204TRB requires one power-supply. the voltage on any input or i/o pin cannot exceed the power pin during power-up. operating range range ambient temperature v cc commercial 0c to +70c +3.3v 5% CYV15G0204TRB dc electrical characteristics parameter description test conditions min. max. unit lvttl-compatible outputs v oht output high voltage i oh = ? 4 ma, v cc = min. 2.4 v v olt output low voltage i ol = 4 ma, v cc = min. 0.4 v i ost output short circuit current v out = 0v [8] , v cc = 3.3v ?20 ?100 ma i ozl high-z output leakage current v out = 0v, v cc ?20 20 a lvttl-compatible inputs v iht input high voltage 2.0 v cc + 0.3 v v ilt input low voltage ?0.5 0.8 v i iht input high current refclkx input, v in = v cc 1.5 ma other inputs, v in = v cc +40 a i ilt input low current refclkx input, v in = 0.0v ?1.5 ma other inputs, v in = 0.0v ?40 a i ihpdt input high current with internal pull-down v in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v ?200 a lvdiff inputs: refclkx v diff [9] input differential voltage 400 v cc mv v ihhp highest input high voltage 1.2 v cc v v illp lowest input low voltage 0.0 v cc /2 v v comref [10] common mode range 1.0 v cc ? 1.2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v i ihh input high current v in = v cc 200 a i imm input mid current v in = v cc /2 ?50 50 a i ill input low current v in = gnd ?200 a differential cml serial outputs: touta1 , touta2 , toutb1 , toutb2 , routc1 , routc2 , routd1 , routd2 v ohc output high voltage (v cc referenced) 100 ? differential load v cc ? 0.5 v cc ? 0.2 v 150 ? differential load v cc ? 0.5 v cc ? 0.2 v 8. tested one output at a time , output shorted for less than one second, less than 10% duty cycle. 9. this is the minimum difference in voltage between the true and co mplement inputs required to ensure detection of a logic-1 or logic-0. a logic-1 exists when the true (+) input is more positive than the complement ( ? ) input. a logic-0 exists when the complement ( ? ) input is more positive than true (+) input. 10. the common mode range defines the allowable range of refclkx+ and refclkx ? when refclkx+ = refclkx ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 21 of 30 v olc output low voltage (v cc referenced) 100 ? differential load v cc ? 1.4 v cc ? 0.7 v 150 ? differential load v cc ? 1.4 v cc ? 0.7 v v odif output differential voltage |(out+) ? (out ? )| 100 ? differential load 450 900 mv 150 ? differential load 560 1000 mv differential serial line receiver inputs: inc1 , inc2 , ind1 , ind2 v diffs [9] input differential voltage |(in+) ? (in ? )| 100 1200 mv v ihe highest input high voltage v cc v v ile lowest input low voltage v cc ? 2.0 v i ihe input high current v in = v ihe max. 1350 a i ile input low current v in = v ile min. ?700 a vi com [11] common mode input range ((v cc ? 2.0v)+0.5)min, (v cc ? 0.5v) max. +1.25 +3.1 v power supply typ. max. i cc [12,13] max power supply current refclkx = max commercial 810 990 ma i cc [12,13] typical power supply current refclkx = 125 mhz commercial 770 950 ma CYV15G0204TRB dc electrical characteristics (continued) parameter description test conditions min. max. unit ac test loads and waveforms 2.0v 0.8v gnd 2.0v 0.8v 80% 20% 80% 20% r l (includes fixture and probe capacitance) 3.0v v th =1.4v 270 ps 270 ps note 15 v th =1.4v 3.3v r1 r2 r1 = 590 ? r2 = 435 ? (includes fixture and probe capacitance) c l 7 pf (a) lvttl output test load r l = 100 ? (b) cml output test load c l (c) lvttl input test waveform (d) cml/lvpecl input test waveform 1ns 1 ns v ihe v ile v ihe v ile note 14 note 14 CYV15G0204TRB ac electrical characteristics parameter description min. max unit CYV15G0204TRB transmitter lvttl switching characteristics over the operating range f ts txclkx clock cycle frequency 19.5 150 mhz t txclk txclkx period=1/f ts 6.66 51.28 ns t txclkh [16] txclkx high time 2.2 ns t txclkl [16] txclkx low time 2.2 ns notes: 11. the common mode range defines the allowable range of input+ and input ? when input+ = input ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 12. maximum i cc is measured with v cc = max, t a = 25c, with all channels and serial line drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded. 13. typical i cc is measured under similar conditions except with v cc = 3.3v, t a = 25c, with all channels enabled and one serial line driver per transmit channel sending a continuous alternating 01 pattern. the redundant output s on each channel are powered down and the parallel outputs ar e unloaded. 14. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only. 15. the lvttl switching threshold is 1.4v. all timing references are made relative to where the signal edges cross the threshold voltage. 16. tested initially and after any design or process changes that may affect t hese parameters, but not 100% tested.
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 22 of 30 t txclkr [16, 17, 18, 19] txclkx rise time 0.2 1.7 ns t txclkf [16, 17, 18, 19] txclkx fall time 0.2 1.7 ns t txds transmit data set-up time to txclkx (txckselx = 0) 2.2 ns t txdh transmit data hold time from txclkx (txckselx = 0) 0.8 ns f tos txclkox clock frequency = 1x or 2x refclkx frequency 19.5 150 mhz t txclko txclkox period=1/f tos 6.66 51.28 ns t txclkod txclko duty cycle centered at 60% high time -1.9 0 ns CYV15G0204TRB receiver lvttl switching characteristics over the operating range f rs rxclkx clock output frequency 9.75 150 mhz t rxclkp rxclkx period = 1/f rs 6.66 102.56 ns t rxclkd rxclkx duty cycle centered at 50% (full rate and half rate) ?1.0 +1.0 ns t rxclkr [16] rxclkx rise time 0.3 1.2 ns t rxclkf [16] rxclkx fall time 0.3 1.2 ns t rxdv? [20] status and data valid time to rxclkx (rxratex = 0) (full rate) 5ui?1.8 [21] ns status and data valid time to rxclkx (rxratex = 1) (half rate) 5ui?1.3 [21] ns t rxdv+ [20] status and data valid time to rxclkx (rxratex = 0) 5ui?1.7 [21] ns status and data valid time to rxclkx (rxratex = 1) 5ui?2.1 [21] ns f ros reclkox clock frequency 19.5 150 mhz t reclko reclkox period=1/f ros 6.66 51.28 ns t reclkod reclkox duty cycle centered at 60% high time -1.9 0 ns CYV15G0204TRB refclkx switching characteristics over the operating range f ref refclkx clock frequency 19.5 150 mhz t refclk refclkx period = 1/f ref 6.6 51.28 ns t refh refclkx high time (txratex = 1)(half rate) 5.9 ns refclkx high time (txratex = 0)(full rate) 2.9 [16] ns t refl refclkx low time (txratex = 1)(half rate) 5.9 ns refclkx low time (txratex = 0)(full rate) 2.9 [16] ns t refd [22] refclkx duty cycle 30 70 % t refr [16, 17, 18, 19] refclkx rise time (20%?80%) 2 ns t reff [16, 17, 18, 19] refclkx fall time (20%?80%) 2 ns t trefds transmit data set-up time to refclkx - full rate (txratex = 0, txckselx = 1) 2.2 ns transmit data set-up time to refclkx - half rate (txratex = 1, txckselx = 1) 1.9 ns notes: 17. the ratio of rise time to falling ti me must not vary by greater than 2:1. 18. for a given operating frequency, neither rise or fall specific ation can be greater than 20% of the clock-cycle period or the data sheet maximum time. 19. all transmit ac timing parameters measured with 1-ns typical rise time and fall time. 20. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 21. receiver ui (unit interval) is calculated as 1/(f ref * 20) (when trgratex = 1) or 1/(f ref * 10) (when trgratex = 0). in an operating link this is equivalent to t b . 22. the duty cycle specification is a simultaneous condition with the t refh and t refl parameters. this means that at faster character rates the refclkx duty cycle cannot be as large as 30%?70%. 23. trgclkx has no phase or frequency relationship with the recovere d clock(s) and only acts as a centering reference to reduce clock synchronization time. trgclkx must be within 1500 ppm ( 0.15%) of the transmitter pll reference (refclkx) frequency. although transmitting to a hotlink ii receiver channel necessitates the frequency difference between the transmitter and re ceiver reference clocks to be within 1500-ppm, the stabili ty of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standa rd. CYV15G0204TRB ac electrical characteristics (continued) parameter description min. max unit
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 23 of 30 t trefdh transmit data hold time from refclkx - full rate (txratex = 0, txckselx = 1) 0.8 ns transmit data hold time from refclkx - half rate (txratex = 1, txckselx = 1) 1.5 ns t refrx [23] trgclkx frequency referenced to received clock period ?0.15 +0.15 % CYV15G0204TRB trgclkx switching characteristics over the operating range f ref trgclkx clock frequency 19.5 150 mhz t refclk trgclkx period = 1/f ref 6.6 51.28 ns t refh trgclkx high time (txratex = 1)(half rate) 5.9 ns trgclkx high time (txratex = 0)(full rate) 2.9 [16] ns t refl trgclkx low time (txratex = 1)(half rate) 5.9 ns trgclkx low time (txratex = 0)(full rate) 2.9 [16] ns t refd [22] trgclkx duty cycle 30 70 % t refr [16, 17, 18, 19] trgclkx rise time (20%?80%) 2 ns t reff [16, 17, 18, 19] trgclkx fall time (20%?80%) 2 ns t refrx [23] trgclkx frequency referenced to received clock frequency ?0.15 +0.15 % CYV15G0204TRB bus configuration write timing characteristics over the operating range t datah bus configuration data hold 0 ns t datas bus configuration data setup 10 ns t wrenp bus configuration wren pulse width 10 ns CYV15G0204TRB jtag test clock characteristics over the operating range f tclk jtag test clock frequency 20 mhz t tclk jtag test clock period 50 ns CYV15G0204TRB device reset characteristics over the operating range t rst device reset pulse width 30 ns CYV15G0204TRB transmitter and reclocke r serial output characteristics over the operating range parameter description condition min. max. unit t b bit time 660 5128 ps t rise [16] cml output rise time 20 ? 80% (cml test load) spdselx = high 50 270 ps spdselx= mid 100 500 ps spdselx =low 180 1000 ps t fall [16] cml output fall time 80 ? 20% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps pll characteristics parameter description condition min. typ. max. unit CYV15G0204TRB transmitter output pll characteristics t jtgensd [16, 24] transmit jitter generation - sd data rate refclkx = 27 mhz 200 ps notes: 24. while sending bist data at the corresponding data rate, af ter 10,000 histogram hits, time referenced to refclkx input. 25. receiver input stream is bist data from the transmit channel . this data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. the measurement was recorded after 10,000 histogram hits, ti me referenced to refclkx of the transmit channel. CYV15G0204TRB ac electrical characteristics (continued) parameter description min. max unit
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 24 of 30 t jtgenhd [16, 24] transmit jitter generation - hd data rate refclkx = 148.5 mhz 76 ps t txlock transmit pll lock to refclkx 200 s CYV15G0204TRB reclocker output pll characteristics t jrgensd [16, 25] reclocker jitter generation - sd data rate trgclkx = 27 mhz 133 ps t jrgenhd [16, 25] reclocker jitter generation - hd data rate trgclkx = 148.5 mhz 107 ps CYV15G0204TRB receive pll characteristics over the operating range t rxlock receive pll lock to input data stream (cold start) 376k ui receive pll lock to input data stream 376k ui t rxunlock receive pll unlock rate 46 ui capacitance [16] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 4 pf pll characteristics parameter description condition min. typ. max. unit CYV15G0204TRB hotlink ii transmitter switching waveforms txclkx txdx[9:0] t txdh t txds t txclk t txclkh t txclkl transmit interface write timing txclkx selected refclkx transmit interface t refclk t refh t refl t trefds t trefdh write timing txratex = 0 txdx[9:0], refclkx selected t trefdh transmit interface write timing txratex = 1 refclkx t refclk t refl t refh note 26 txdx[9:0] t trefds t trefds t trefdh refclkx selected
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 25 of 30 CYV15G0204TRB hotlink ii transmitter switching waveforms (continued) txclkox t txclko transmit interface txclkox timing txratex = 1 (internal) refclkx t refclk t refl t refh note 27 note 28 txclkox t txclko transmit interface txclkox timing refclkx note27 note28 t refclk t refh t refl txratex = 0 switching waveforms for the CYV15G0204TRB hotlink ii receiver notes: 26. when refclkx is configured for half-rate operation (txratex = 1) and data is captured using refclkx instead of a txclkx clo ck. data is captured using both the rising and falling edges of refclkx. 27. the txclkox output remains at the character rate regardless of the state of txratex and does not follow the duty cycle of re fclkx. 28. the rising edge of txclkox output has no dire ct phase relationship to the refclkx input. rxclkx+ rxdx[9:0] t rxdv+ t rxclkp r eceive interface r ead timing rxclkx- t rxdv ? r xratex = 0
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 26 of 30 switching waveforms for the CYV15G0204TRB hotlink ii receiver rxclkx+ rxdx[9:0] t rxdv+ t rxdv ? t rxclkp receive interface read timing rxclkx- rxratex = 1 addr[3:0] t datas bus configuration write timing data[6:0] wren t datah t wrenp
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 27 of 30 table 7. package coordinate signal allocation ball id signal name signal type ball id signal name signal type ball id signal name signal type a01 inc1? cml in c07 ulcc lvttl in pu f17 nc no connect a02 routc1? cml out c08 gnd ground f18 nc no connect a03 inc2? cml in c09 data[6] lvtt l in pu f19 txclkob lvttl out a04 routc2? cml out c10 data[4] lvttl in pu f20 nc no connect a05 vcc power c11 data[2] lvttl in pu g01 gnd ground a06 ind1? cml in c12 data[0] lvttl in pu g02 wren lvttl in pu a07 routd1? cml out c13 gnd ground g03 gnd ground a08 gnd ground c14 nc no connect g04 gnd ground a09 ind2? cml in c15 spdseld 3-l evel sel g17 spdselb 3-level sel a10 routd2? cml out c16 vcc power g18 nc no connect a11 gnd ground c17 ldtden lvttl in pu g19 spdsela 3-level sel a12 touta1? cml out c18 trst lvttl in pu g20 nc no connect a13 gnd ground c19 gnd ground h01 gnd ground a14 gnd ground c20 tdo lvttl 3-s out h02 gnd ground a15 touta2? cml out d01 tclk lvttl in pd h03 gnd ground a16 vcc power d02 reset lvttl in pu h04 gnd ground a17 vcc power d03 inseld lvttl in h17 gnd ground a18 toutb1? cml out d04 vcc power h18 gnd ground a19 vcc power d05 vcc power h19 gnd ground a20 toutb2? cml out d06 vcc power h20 gnd ground b01 inc1+ cml in d07 spdselc 3-level sel j01 gnd ground b02 routc1+ cml out d08 gnd ground j02 gnd ground b03 inc2+ cml in d09 data[5] lvttl in pu j03 gnd ground b04 routc2+ cml out d10 data[3] lvttl in pu j04 gnd ground b05 vcc power d11 data[1] lvttl in pu j17 nc no connect b06 ind1+ cml in d12 gnd ground j18 nc no connect b07 routd1+ cml out d13 gnd ground j19 nc no connect b08 gnd ground d14 gnd ground j20 nc no connect b09 ind2+ cml in d15 nc no connect k01 rxdc[4] lvttl out b10 routd2+ cml out d16 vcc power k02 trgclkc? pecl in b11 nc no connect d17 nc no connect k03 gnd ground b12 touta1+ cml out d18 vcc power k04 gnd ground b13 gnd ground d19 scanen2 lvttl in pd k17 nc no connect b14 nc no connect d20 tmen3 lvttl in pd k18 nc no connect b15 touta2+ cml out e01 vcc power k19 nc no connect b16 vcc power e02 vcc power k20 nc no connect b17 nc no connect e03 vcc power l01 rxdc[5] lvttl out b18 toutb1+ cml out e04 vcc power l02 trgclkc+ pecl in b19 nc no connect e17 vcc power l03 lfic lvttl out b20 toutb2+ cml out e18 vcc power l04 gnd ground c01 tdi lvttl in pu e19 vcc power l17 nc no connect c02 tms lvttl in pu e20 vcc power l18 nc no connect c03 inselc lvttl in f01 rxdc[8] lvttl out l19 nc no connect
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 28 of 30 c04 vcc power f02 rxdc[9] lvttl out l20 txdb[6] lvttl in c05 vcc power f03 vcc power m01 rxdc[6] lvttl out c06 ulcd lvttl in pu f04 vcc power m02 rxdc[7] lvttl out m03 vcc power u03 vcc power w03 lfid lvttl out m04 repdoc lvttl out u04 vcc power w04 rxclkd? lvttl out m17 refclkb+ pecl in u05 vcc power w05 vcc power m18 refclkb? pecl in u06 rxdd[4] lvttl out w06 rxdd[6] lvttl out m19 txerrb lvttl out u07 rxdd[3] lvttl out w07 rxdd[0] lvttl out m20 txclkb lvttl in pd u08 gnd ground w08 gnd ground n01 gnd ground u09 txda[9] lvttl in w09 addr [3] lvttl in pu n02 gnd ground u10 addr [0] lvttl in pu w10 addr [1] lvttl in pu n03 gnd ground u11 trgclkd? pecl in w11 nc no connect n04 gnd ground u12 txda[1] lvttl in w12 txerra lvttl out n17 gnd ground u13 gnd ground w13 gnd ground n18 gnd ground u14 txda[4] lv ttl in w14 txda[2] lvttl in n19 gnd ground u15 txda[8] lv ttl in w15 txda[6] lvttl in n20 gnd ground u16 vcc power w16 vcc power p01 rxdc[3] lvttl out u17 nc no connect w17 nc no connect p02 rxdc[2] lvttl out u18 txdb[8 ] lvttl in w18 refclka+ pecl in p03 rxdc[1] lvttl out u19 nc no connect w19 nc no connect p04 rxdc[0] lvttl out u20 nc no connect w20 nc no connect p17 txdb[5] lvttl in v01 vcc power y01 vcc power p18 txdb[4] lvttl in v02 vcc power y02 vcc power p19 txdb[3] lvttl in v03 vcc power y03 rxdd[9] lvttl out p20 txdb[2] lvttl in v04 rxdd[8] lvttl out y04 rxclkd+ lvttl out r01 biststc lvttl out v05 vcc power y05 vcc power r02 reclkoc lvttl out v06 rxdd[5] lvttl out y06 rxdd[7] lvttl out r03 rxclkc+ lvttl out v07 rxdd[1] lvttl out y07 rxdd[2] lvttl out r04 rxclkc? lvttl out v08 gnd ground y08 gnd ground r17 txdb[1] lvttl in v09 biststd lv ttl out y09 reclkod lvttl out r18 txdb[0] lvttl in v10 addr [2 ] lvttl in pu y10 nc no connect r19 txdb[9] lvttl in v11 trgclkd + pecl in y11 txclka lvttl in pd r20 txdb[7] lvttl in v12 txclk oa lvttl out y12 nc no connect t01 vcc power v13 gnd ground y13 gnd ground t02 vcc power v14 txda[3] lvttl in y14 txda[0] lvttl in t03 vcc power v15 txda[7] lvttl in y15 txda[5] lvttl in t04 vcc power v16 vcc power y16 vcc power t17 vcc power v17 nc no connect y17 repdod lvttl out t18 vcc power v18 nc no connect y18 refclka? pecl in t19 vcc power v19 nc no connect y19 nc no connect t20 vcc power v20 nc no connect y20 nc no connect u01 vcc power w01 vcc power u02 vcc power w02 vcc power table 7. package coordinate signal allocation (continued) ball id signal name signal type ball id signal name signal type ball id signal name signal type
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 29 of 30 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. hotlink is a registered trademark and hotlink ii is a trademar k of cypress semiconductor. all product and company names mentioned in this document may be the tr ademarks of their respective holders. ordering information speed ordering code package name package type operating range standard CYV15G0204TRB-bgc bl256 256-ball ther mally enhanced ball grid array commercial package diagram 256-lead l2 ball grid array (27 x 27 x 1.57 mm) bl256 51-85123-*e
preliminary CYV15G0204TRB document #: 38-02101 rev. ** page 30 of 30 document history page document title: CYV15G0204TRB independ ent clock hotlink ii? dual serializer and dual reclocking deserializer document number: xx-xxxxx rev. ecn no. issue date orig. of change description of change ** fre new data sheet

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